Post-Training
Investigating self-improving models, reasoning optimization, synthetic data generation, and feedback-driven learning to advance coding, reasoning, and task-specific intelligence.
We develop methods to make AI models more capable, efficient, and faster to run.
Explore our missionWe are developing Sinefour Intelligence, a unified research initiative connecting post-training, intelligence optimization, and inference acceleration. Our aim is to advance what models can do while reducing the compute, memory, and time they need.
One research initiative across three connected directions: improving capability, optimizing computation, and accelerating execution.
Investigating self-improving models, reasoning optimization, synthetic data generation, and feedback-driven learning to advance coding, reasoning, and task-specific intelligence.
Exploring model compression, quantization, adaptive optimization, and hardware-aware optimization to improve AI performance and computational efficiency.
Exploring high-throughput token generation through compute-memory co-design, optimized dataflow, compiler-driven execution, and specialized inference architectures.
Early-stage experiments and prototypes across AI execution and engineering. This work informs our direction.
Workload-driven architecture search spanning throughput, energy, bandwidth, and physical constraints.
Architecture search evaluated 3,000 candidates across a 7,056-configuration design space, modeling decode throughput, energy, and hardware constraints.
Component-level switching experiments and a separate scaled RTL-to-GDS physical-design implementation.
Completed 2,000 randomized RTL/gate test cycles with zero mismatches, measured mapped-net switching activity, and developed a separate 256-PE SKY130HD physical-design prototype.
Developed a model-specific fixed-weight inference architecture for Qwen2.5-Coder-3B-Instruct, compiled its 36-layer RTL design, and validated execution checkpoints through hardware simulation.
Qwen2.5-Coder-3B-Instruct · Research architecture and saved RTL evidence
From coding-model experiments and TVM compiler exploration to ASIC RTL simulation, our research has delivered a compiled 36-layer design, verified execution results, and measured cycle improvements across bounded tests.
Research conversations, collaborations, and new ideas start here.